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STM8S103XX STM8S105xx
Access line, STM8S 8-bit MCU, up to 32 Kbytes Flash, 10-bit ADC, timers, USART, SPI, IC
Preliminary Data
Features
Core

Max fCPU: up to 16 MHz Advanced STM8 core with Harvard architecture and 3-stage pipeline Extended instruction set
LQFP48 7x7
LQFP44 10x10
Memories
Program memory: Up to 32 Kbytes Flash; data retention 20 years at 85C after 1 kcycles RAM: Up to 2 Kbytes
LQFP32 7x7
TSSOP20
VFQFN32 5x5
Communications interfaces
Clock, reset and supply management

3.0 to 5.5 V operating voltage
Flexible clock control, 4 master clock sources: - Low power crystal resonator oscillator - External clock input - Internal 16 MHz RC - Internal low power 128 kHz RC Clock security system with clock monitor Power management: - Low power modes (Wait, Active-halt, Halt) - Switch-off peripheral clocks individually Permanently active, low consumption poweron and power-down reset
USART or LINUART with clock output for synchronous operation, smartcard mode, IrDA mode, LIN master mode SPI synchronous serial interface up to 8 Mbit/s 2 I C interface up to 400 Kbit/s
Analog to digital converter (ADC)
10-bit, 1 LSB ADC with up to 10 multiplexed channels, scan mode and analog watchdog
I/Os
Up to 38 I/Os on a 48-pin package including 9 high sink outputs Highly robust I/O design, immune against current injection Table 1.
Reference STM8S103XX STM8S105xx
Interrupt management
Device summary
Root part number STM8S103K3 STM8S105C6, STM8S105C4, STM8S105K6, STM8S105K4, STM8S105S6, STM8S105S4,
Nested interrupt controller with 32 interrupts Up to 37 external interrupts on 6 vectors
Timers

2x 16-bit general purpose timers, with 2+3 CAPCOM channels (IC, OC or PWM) Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization 8-bit basic timer with 8-bit prescaler Auto wake-up timer 2 watchdog timers: Window watchdog and independent watchdog
June 2008
Rev 2
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www.st.com 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
STM8S103XX, STM8S105xx
Contents
1 2 3 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 11 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Auto wake-up counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TIM2- 16-bit general purpose timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Analog/digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.14.1 4.14.2 4.14.3 4.14.4 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 LINUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 5.2 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.1 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Contents
7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2 7.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.3.1 7.3.2 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.1.1 8.1.2 8.1.3 LQFP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 QFN package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 TSSOP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9 10
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1 10.2 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 53 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.2.1 10.2.2 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.3
Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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List of tables
STM8S103XX, STM8S105xx
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM8S103/105 access line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STM8 TIM timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Legend/abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin description for STM8S105 MCUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin description for STM8S103 MCUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 STM8S103x alternate function remapping bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 32-lead very thin fine pitch quad flat no-lead package mechanical data . . . . . . . . . . . . . . 50 TSSOP 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data . . . . . . . . . . . . . . . . . . . . 51 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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STM8S103XX, STM8S105xx
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. STM8S105 access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 STM8S103 access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash memory organization (STM8S105) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Flash memory organisation (STM8S103) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 LQFP 44-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STM8S105 LQFP/VQFN 32-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM8S103 LQFP/VQFN 32-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 TSSOP20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Typical VIL and VIH vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Typical pull-up resistance RPU vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 40 Typical pull-up current Ipu vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Typ. VOL @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typ. VOL @ VDD = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typ. VOL @ VDD = 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typ. VOL @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typ. VDD - VOH @ VDD = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Typ. VDD - VOH @ VDD = 5.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Typ. VDD - VOH @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Typical NRST VIL and VIH vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Typical NRST pull-up resistance RPU vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . 45 Typical NRST pull-up current Ipu vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . 45 Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 44-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 32-lead very thin fine pitch quad flat no-lead package (5 x 5) . . . . . . . . . . . . . . . . . . . . . . 50 TSSOP 20-pin, 4.40 mm body, 0.65 mm pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 STM8S103/105 access line ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . 52
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Introduction
STM8S103XX, STM8S105xx
1
Introduction
This datasheet contains the description of the STM8S103/105 access line features, pinout, electrical characteristics, mechanical data and ordering information.
For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016) For information on programming, erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual (PM0051) For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470) For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044)

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STM8S103XX, STM8S105xx
Description
2
Description
The STM8S103/105 access line 8-bit microcontrollers offer from 8 Kbytes up to 32 Kbytes of program memory. All devices of the STM8S103/105 access line provide the following benefits:
Reduced system cost - High system integration level with internal clock oscillators, watchdog and brownout reset 16 MHz CPU clock frequency Robust I/O, independent watchdogs with separate clock source Clock security system Applications scalability across a common family product architecture with compatible pinout, memory map and and modular peripherals. Full documentation and a wide choice of development tools Advanced core and peripherals made in a state-of-the art technology A family of products for applications with 3.0 V to 5.5 V operating supply
Performance and robustness - - -
Short development cycles - -
Product longevity - -
Table 2.
STM8S103/105 access line features
Timer CAPCOM channels A/D Converter channels Flash Program memory (bytes) No. of maximum GPIO (I/O) Timer PWM channels Ext. Interrupt pins
Device
RAM (bytes)
Pin count
Peripheral set
STM8S105C6 STM8S105C4 STM8S105S6 STM8S105S4 STM8S105K6 STM8S105K4
48 48 44 44 32 32
38(1) 38(1) 34(1) 34(1) 25(1) 25(1)
37 37 31 31 23 23
9 9 8 8 8 8
12 10 12 10 11 9 11 9 11 7 11 7
32K 16K 32K 16K 32K 16K
2K LINUART + extended 2K features (synchronous 2K comm. smartcard 2K mode, IrdA mode), 2K PWM timer (TIM3) 2K
STM8S103K3 32 28(2) 28
7
10
7
8
Multipurpose timer (TIM1), PWM timer (TIM2), 8-bit timer (TIM4), SPI, I2C USART with full Window WDG, features (synchronous Independent WDG, 1K comm. smartcard ADC + extended features mode, IrdA mode and single wire mode)
1. 9 high sink outputs 2. 8 high sink outputs
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Block diagram
STM8S103XX, STM8S105xx
3
Block diagram
Figure 1. STM8S105 access line block diagram
Reset block Clock controller Reset Reset
XTAL 1-16 MHz
RC int. 16 MHz Detector POR BOR RC int. 128 kHz
Clock to peripherals and core
Window WDG STM8 CORE Independent WDG Single wire debug interf. Master/slave autosynchro LIN master SPI emul. 400 Kbit/s
Debug/SWIM
Up to 32 Kbytes program Flash
LINUART + extended features
Address and data bus
I2C
Up to 2 Kbytes RAM Boot ROM
10 Mbit/s
SPI
16-bit advanced control timer (TIM1) 16-bit general purpose timers (TIM2, TIM3) 8-bit basic timer (TIM4)
Up to 9 CAPCOM channels
Up to 10 channels
10-bit ADC + extended features
1/2/4 kHz beep
Beeper
AWU timer
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STM8S103XX, STM8S105xx Figure 2. STM8S103 access line block diagram
Block diagram
Reset block Clock controller Reset Reset
XTAL 1-16 MHz
RC int. 16 MHz Detector POR BOR RC int. 128 kHz
Clock to peripherals and core
Window WDG STM8 CORE Independent WDG Single wire debug interf.
Debug/SWIM
Up to 8 Kbytes program Flash
400 Kbit/s
Address and data bus
I2C
1 Kbytes RAM Boot ROM
8 Mbit/s
SPI
LIN master SPI emul.
USART
16-bit advanced control timer (TIM1) 16-bit general purpose timer (TIM2) 8-bit basic timer (TIM4)
Up to 7 CAPCOM channels
Up to 7 channels
10-bit ADC + extended features
1/2/4 kHz beep
Beeper
AWU timer
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Product overview
STM8S103XX, STM8S105xx
4
Product overview
The following section intends to give an overview of the basic features of the STM8S103/105 access line functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016).
4.1
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance. It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers

Harvard architecture 3-stage pipeline 32-bit wide program memory bus - single cycle fetching for most instructions X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter - 16-Mbyte linear memory space 16-bit stack pointer - access to a 64 K-level stack 8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing

20 addressing modes Indexed indirect addressing mode for look-up tables located anywhere in the address space Stack pointer relative addressing mode for local variables and parameter passing
Instruction set

80 instructions with 2-byte average instruction size Standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division Bit manipulation Data transfer between stack and accumulator (push/pop) with direct stack access Data transfer using the X and Y registers or direct memory-to-memory transfers
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STM8S103XX, STM8S105xx
Product overview
4.2
Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module and permit non-intrusive, real-time incircuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.

R/W to RAM and peripheral registers in real-time R/W access to all resources by stalling the CPU Breakpoints on all program-memory instructions (software breakpoints) 2 advanced breakpoints, 23 predefined configurations
4.3
Interrupt controller

Nested interrupts with 3 software priority levels 32 interrupt vectors with hardware priority Up to 37 external interrupts on 6 vectors including TLI Trap and reset interrupts
4.4
Flash program memory

Up to 32 Kbytes of program single voltage Flash memory User option byte area
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Product overview
STM8S103XX, STM8S105xx
Write protection (WP)
Write protection of Flash is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. There are two levels of write protection. The first level is known as MASS (Memory Access Security System). MASS is always enabled and protects the main Flash program memory and option bytes. To perform In-Application Programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to modify the contents of main program memory or the device option bytes. A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to Figure 3. The size of the UBC is programmable through the UBC option byte (Table 8.), in increments of 1 page, by programming the UBC option byte in ICP mode. This divides the program memory into two areas:

Main program memory: Up to 32 Kbytes minus UBC User-specific boot code (UBC): Configurable up to 32 Kbytes
The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines. Figure 3. Flash memory organization (STM8S105)
UBC area Remains write protected during IAP Up to 32 Kbytes Flash program memory
Programmable area from 0.5 Kbytes (2 first pages) up to 32 Kbytes (1 page steps)
Program memory area Write access possible for IAP
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STM8S103XX, STM8S105xx Figure 4. Flash memory organisation (STM8S103)
Product overview
UBC area Remains write protected during IAP Up to 8 Kbytes Flash program memory
Programmable area from 128 bytes (2 first pages) up to 8 Kbytes (1 page steps)
Program memory area Write access possible for IAP
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory in debug mode. Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.
4.5
Clock controller
The clock controller distributes the system clock (fMASTER) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.
Features
Clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching. Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. Master clock sources: 4 different clock sources can be used to drive the master clock: - - - - 1-16 MHz High Speed External crystal (HSE) Up to 16 MHz High Speed user-external clock (HSE user-ext) 16 MHz High Speed Internal RC oscillator (HSI) 128 kHz Low Speed Internal RC (LSI)

Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. Clock security system (CSS): This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS
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Product overview and an interrupt can optionally be generated.
STM8S103XX, STM8S105xx
Configurable main clock output (CCO): This outputs an external clock for use by the application. Available frequencies are 8 MHz, 4 MHz or 1 MHz.
4.6
Power management
For efficent power management, the application can be put in one four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources.

Wait mode: in this mode, the CPU is stopped, but peripherals are kept running. The wake-up is performed by an internal or external interrupt or reset. Fast active halt mode: in this mode, the CPU and peripheral clocks are stopped. An internal wake-up is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is more than in slow active halt mode, but the wake-up time is faster. Wake-up is triggered by the internal AWU interrupt, external interrupt or reset. Slow active halt mode: this mode is the same as fast active halt except that the main voltage regulator is powered off, so the wake up time is slower. Halt mode: in this mode the microcontroller uses the least power, CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wake-up is triggered by external interrupt or reset.

4.7
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to the applications. The WDG timer activity is controlled by option bytes. Once activated the watchdog can not be disabled by the user program without reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. The window function can be used to trim the watchdog behavior to match the application perfectly. The application software must refresh the counter before time-out and during a limited time window. A reset is generated in two situations: 1. 2. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 s up to 64 ms. Refresh out of window: The downcounter is refreshed before its value is lower then the one stored in the window register.
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures.
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STM8S103XX, STM8S105xx
Product overview
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 s to 1 s.
4.8
Auto wake-up counter

Used for auto wake-up from active halt mode Clock source: internal 128 kHz internal low frequency RC oscillator or external clock
4.9
Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.
4.10
TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver.

16-bit up, down and up/down autoreload counter with 16-bit prescaler 4 independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output Synchronization module to control the timer with external signal Break input to force the timer outputs into a defined state 3 complementary outputs with adjustable dead time Encoder mode Interrupt sources: x input capture/output compare, 1 x overflow/update, 1 x break

4.11
TIM2- 16-bit general purpose timer

16-bit autoreload (AR) up-counter 15-bit prescaler adjustable to fixed power of 2 ratios 1...32768 Timers with 3 or 2 individually configurable capture/compare channels PWM mode Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
4.12
TIM4 - 8-bit basic timer

8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 Clock source: CPU clock Interrupt source: 1 x overflow/update
15/56
Product overview Table 3. STM8 TIM timer feature comparison
Counter size (bits) 16 16 16 8
STM8S103XX, STM8S105xx
Timer
Prescaler
Ext. Counting CAPCOM Complem. trigger mode channels outputs Up/down Up Up Up 4 3 2 0 3 0 0 0 Yes No
Timer synchronization/ chaining
TIM1 TIM2 TIM3 TIM4
Any integer from 1 to 65536 Any power of 2 from 1 to 32768 Any power of 2 from 1 to 32768 Any power of 2 from 1 to 128
Yes No No
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STM8S103XX, STM8S105xx
Product overview
4.13
Analog/digital converter (ADC)
STM8S103/105 access line products contain a 10-bit successive approximation A/D converter with up to 10 multiplexed input channels and the following general features: - - - - - - - Input voltage range: 0 to VDDA Dedicated voltage reference (VREF) pins available on 80 and 64-pin devices Conversion time: 14 clock cycles Single and continuous conversion modes External trigger input Trigger from TIM1 TRGO (STM8S105) or TIM2 TRGO (STM8S103) End of conversion (EOC) interrupt
ADC extended features
STM8S103/105 access line products contain a 10-bit successive approximation A/D converter with the following features: - - - - - - Up to 10 (STM8S105x) or 7 (STM8S103x) multiplexed input channels Single, continuous and buffered continuous conversion on a selected channel Scan mode for single and continuous conversion of a sequence of channels Analog watchdog capability with programmable upper and lower thresholds Internal reference voltage on channel AIN7 (STM8S103 only) Analog watchdog interrupt
4.14
Communication interfaces
The following communication interfaces are implemented:
USART: - - STM8S105: no USART STM8S103: full feature UART, single wire mode, LIN2.1 master capability STM8S105: LIN2.1 master/slave capability, full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA mode STM8S103: No LINUART
LINUART: - -

SPI - full and half-duplex, 8 Mbit/s IC - up to 400 Kbit/s
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Product overview
STM8S103XX, STM8S105xx
4.14.1
USART
Main features

1 Mbit/s full duplex SCI LIN master capable SPI emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder Single wire half duplex mode
Asynchronous communication (UART mode)

Full duplex communication - NRZ standard format (mark/space) Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver 2 receiver wakeup modes: - - Address bit (MSB) Idle line (interrupt)

Transmission error detection with interrupt generation Parity control
LIN master capability

Emission: Generates 13-bit synch break frame Reception: Detects 11-bit break frame
Synchronous communication

Full duplex synchronous transfers SPI master operation 8-bit data communication Max. speed: 1 Mbit/s at 16 MHz (fCPU/16)
4.14.2
LINUART
Main features

LIN master/slave rev. 2.1 compliant Auto-synchronization in LIN slave mode High precision baud rate generator 1 Mbit full duplex SCI
LIN master

Emission: Generates 13-bit synch break frame Reception: Detects 11-bit break frame
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STM8S103XX, STM8S105xx
Product overview
LIN slave

Autonomous header handling - one single interrupt per valid message header Automatic baud rate synchronization - maximum tolerated initial clock deviation 15 % Synch delimiter checking 11-bit LIN synch break detection - break detection always active Parity check on the LIN identifier field LIN error management Hot plugging support
Asynchronous communication (UART mode)

Full duplex, asynchronous communications - NRZ standard format (mark/space) Independently programmable transmit and receive baud rates up to 500 Kbit/s Programmable data word length (8 or 9 bits) Low-power standby mode - 2 receiver wake-up modes: - - Address bit (MSB) Idle line

Muting function for multiprocessor configurations Overrun, noise and frame error detection 6 interrupt sources Tx, Rx parity control
Note:
In STM8S105, the LINUART also supports IrDA mode, Smartcard mode and synchronous communication (SPI master mode).
4.14.3
SPI

Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on 2 lines with a possible bidirectional data line Master or slave operation - selectable by hardware or software CRC calculation 1 byte Tx and Rx buffer Slave/master selection input pin
19/56
Product overview
STM8S103XX, STM8S105xx
4.14.4
I2C
I2C master features: - - Clock generation Start and stop generation slave features: Programmable I2C address detection Stop bit detection
I2C - -

Generation and detection of 7-bit/10-bit addressing and general call Supports different communication speeds: - - Standard speed (up to 100 kHz), Fast speed (up to 400 kHz)
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STM8S103XX, STM8S105xx
Pinouts and pin description
5
5.1
Pinouts and pin description
Package pinouts
Figure 5. LQFP 48-pin pinout
PD7/TLI PD6/LINUART_RX PD5/LINUART_TX PD4 (HS)/TIM2_CC1/BEEP PD3 (HS)/TIM2_CC2/ADC_ETR PD2 (HS)/TIM3_CC1 PD1 (HS)/SWIM PD0 (HS)/TIM3_CC2 PE0/CLK_CCO PE1/I2C_SCL PE2/I2C_SDA PE3/TIM1_BKIN NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 TIM2_CC3/PA3 PA4 PA5 PA6 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 2223 24 VDDA VSSA AIN7/PB7 AIN6/PB6 AIN5/PB5 AIN4/PB4 TIM1_ETR/AIN3/PB3 TIM1_NCC3/AIN2/PB2 TIM1_NCC2/AIN1/PB1 TIM1_NCC1/AIN0/PB0 AIN8/PE7 AIN9/PE6 PG1 PG0 PC7/SPI_MISO PC6/SPI_MOSI VDDIO_2 VSSIO_2 PC5/SPI_SCK PC4 (HS)/TIM1_CC4 PC3 (HS)/TIM1_CC3 PC2 (HS)/TIM1_CC2 PC1 (HS)/TIM1_CC1/LINUART_CK PE5/SPI_NSS
(HS) high sink capability
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Pinouts and pin description Figure 6. LQFP 44-pin pinout
STM8S103XX, STM8S105xx
NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 PA4 PA5 PA6
44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 VDDA VSSA AIN7/PB7 AIN6/PB6 AIN5/PB5 AIN4/PB4 TIM1_ETR/AIN3/PB3 TIM1_NCC3/AIN2/PB2 TIM1_NCC2/AIN1/PB1
TIM1_NCC1/AIN0/PB0
PD7/TLI/TIM1_CC4 PD6/LINUART_RX PD5/LINUART_TX PD4 (HS)/TIM2_CC1/BEEP PD3 (HS)/TIM2_CC2/ADC_ETR PD2 (HS)/TIM3_CC1/TIM2_CC3 PD1 (HS)/SWIM PD0 (HS)/TIM3_CC2/TIM1_BRK PE0/CLK_CCO PE1/I2C_SCL PE2/I2C_SDA PG1 PG0 PC7/SPI_MISO PC6/SPI_MOSI VDDIO_2 VSSIO_2 PC5/SPI_SCK PC3 (HS)/TIM1_CC3 PC2 (HS)/TIM1_CC2 PC1 (HS)/TIM1_CC1/LINUART_CK PE5/SPI_NSS AIN9/PE6
(HS) high sink capability
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STM8S103XX, STM8S105xx Figure 7. STM8S105 LQFP/VQFN 32-pin pinout
PD7/TLI PD6/LINUART_RX PD5/LINUART_TX PD4 (HS)/TIM2_CC1/BEEP PD3 (HS)/TIM2_CC2/ADC_ETR PD2 (HS)/TIM3_CC1/TIM2_CC3 PD1 (HS)/SWIM PD0 (HS)/TIM3_CC2/CLK_CCO/TIM1_BRK
Pinouts and pin description
NRST OSCIN/PA1 OSCOUT/PA2 VSS VCAP VDD VDDIO AIN12/PF4
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 1516 VDDA VSSA I2C_SDA/AIN5/PB5 I2C_SCL/AIN4/PB4 TIM1_ETR/AIN3/PB3 TIM1_NCC3/AIN2/PB2 TIM1_NCC2/AIN1/PB1 TIM1_NCC1/AIN0/PB0
PC7/SPI_MISO PC6/SPI_MOSI PC5/SPI_SCK PC4 (HS)/TIM1_CC4 PC3 (HS)/TIM1_CC3 PC2 (HS)/TIM1_CC2 PC1 (HS)/TIM1_CC1/LINUART_CK PE5/SPI_NSS
(HS) high sink capability
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Pinouts and pin description Figure 8. STM8S103 LQFP/VQFN 32-pin pinout
STM8S103XX, STM8S105xx
NRST OSCIN/PA1 OSCOUT/PA2 VSS VCAP VDD SPI_NSS/TIM2_CC3/(HS)PA3 PF4
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 1516 PB7 PB6 I2C_SDA/PB5 I2C_SCL/PB4 TIM1_ETR/PB3 TIM1_NCC3/(HS)PB2 TIM1_NCC2/AIN1/(HS)PB1 TIM1_NCC1/AIN0/(HS)PB0
PD7(HS)/TLI/TIM1_CC4 PD6/AIN5/USART_RX PD5/AIN4/USART_TX PD4 (HS)/TIM2_CC1/BEEP /USART_CK PD3 (HS)/AIN4/TIM2_CC2/ADC_ETR PD2 (HS)/AIN3/TIM2_CC3 PD1 (HS)/SWIM PD0 (HS)/TIM1_BKIN/CLK_CCO PC7(HS)/SPI_MISO PC6(HS)/SPI_MOSI PC5(HS)/SPI_SCK/TIM2_CC1 PC4(HS)/AIN2/TIM1_CC4 PC3 (HS)/TIM1_CC3/TLI/USART_CK PC2 (HS)/TIM1_CC2 PC1 (HS)/TIM1_CC1 PE5(HS)/SPI_NSS
(HS) high sink capability
Figure 9.
TSSOP20 pinout
USART_TX/AIN5/PD5 USART_RX/AIN6/PD6 NRST OSCIN/PA1 OSCOUT/PA2 VSS VCAP VDD SPI_NSS/TIM2_CC3/(HS)PA3 I2C_SDA/PB5
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
PD4 (HS)/TIM2_CC1/BEEP /USART_CK PD3 (HS)/AIN4/TIM2_CC2/ADC_ETR PD2(HS)/AIN3/TIM2_CC3 PD1 (HS)/SWIM PC7(HS)/SPI_MISO PC6(HS)/SPI_MOSI PC5 (HS)/TIM2_CC1/SPI_SCK PC4(HS)/AIN2/TIM1_CC4/CLK_CCO PC3(HS)/TLI/TIM1_CC3/USART_CK PB4/I2C_SCL
(HS) high sink capability
24/56
STM8S103XX, STM8S105xx
Pinouts and pin description
5.2
Pin description
Table 4.
Type Level
Legend/abbreviations
I= input, O = output, S = power supply Input Output CM = CMOS HS = High sink
Output speed
O1 = Slow (up to 2 MHz) O2 = Fast (up to 10 MHz) O3 = Fast/slow programmability with slow as default state after reset O4 = Fast/slow programmability with fast as default state after reset float = floating, wpu = weak pull-up T = true open drain, OD = open drain, PP = push pull
Port and control Input configuration Output
Reset state is shown in bold. Table 5.
Pin number Type LQFP48 LQFP44 LQFP32
Pin description for STM8S105 MCUs
Main function (after reset) Reset O1 X X O1 X X Port A1 X Port A2 Resonator/ crystal in Resonator/ crystal out I/O ground Digital ground 1.8 V regulator capacitor Digital power supply I/O power supply X X X X X X X X X O1 X O1 X O3 X O3 X O3 X X Port F4 Analog input 12 TIM3_CC1 [AFR1] Input Ext. interrupt High sink floating Output Alternate Default alternate function after function remap [option bit]
Speed
wpu
OD
Pin name
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9
1 NRST 2 PA1/OSCIN 3 PA2/OSCOUT - VSSIO_1 4 VSS 5 VCAP 6 VDD 7 VDDIO_1 8 PF4/AIN12 - PA3/TIM2_CC3 - PA4 - PA5 - PA6 9 VDDA
I/O I/O X I/O X S S S S S I/O X I/O X I/O X I/O X I/O X S S I/O X
X X X
X Port A3 Timer 2 - channel3 X Port A4 X Port A5 X Port A6 Analog power supply Analog ground
11 10 12 11 13 12
14 13 10 VSSA 15 14 - PB7/AIN7
X
X
O1 X
X Port B7 Analog input 7
PP
25/56
Pinouts and pin description Table 5.
Pin number Type LQFP48 LQFP44 LQFP32
STM8S103XX, STM8S105xx
Pin description for STM8S105 MCUs (continued)
Main function (after reset) Input Ext. interrupt High sink floating Output Alternate Default alternate function after function remap [option bit]
Speed
wpu
OD
Pin name
16 15
- PB6/AIN6
I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X
X X X X X X X X X X
X X X X X X X X X X
O1 X O1 X O1 X O1 X O1 X O1 X O1 X O1 X O1 X O1 X
X Port B6 Analog input 6 X Port B5 Analog input 5 X Port B4 Analog input 4 X Port B3 Analog input 3 X Port B2 Analog input X Port B1 Analog input 1 X Port B0 Analog input 0 X X X Port E7 Analog input 8 Port E7 Analog input 9 Port E5 SPI master/slave select I2C_SDA [AFR6] I2C_SCL [AFR6] TIM1_ETR [AFR5] TIM1_NCC3 [AFR5] TIM1_NCC2 [AFR5] TIM1_NCC1 [AFR5]
17 16 11 PB5/AIN5 18 17 12 PB4/AIN4 19 18 13 PB3/AIN3 20 19 14 PB2/AIN2 21 20 15 PB1/AIN1 22 21 16 PB0/AIN0 23 - PE7/AIN8 PE6/AIN9
24 22
25 23 17 PE5/SPI_NSS PC1/TIM1_CC1/ LINUART_CK
26 24 18
I/O X I/O X I/O X I/O X I/O X S S I/O X I/O X I/O X I/O X I/O X I/O X
X X X X X
X HS O3 X X HS O3 X X HS O3 X X HS O3 X X O3 X
Timer 1 - channel 1 X Port C1 / LINUART synchronous clock X Port C2 Timer 1- channel 2 X Port C3 Timer 1 - channel 3 X Port C4 Timer 1 - channel 4 X Port C5 SPI clock I/O ground I/O power supply
27 25 19 PC2/TIM1_CC2 28 26 20 PC3/TIM1_CC3 29 21 PC4/TIM1_CC4
30 27 22 PC5/SPI_SCK 31 28 32 29 - VSSIO_2 - VDDIO_2
PP
33 30 23 PC6/SPI_MOSI 34 31 24 PC7/SPI_MISO 35 32 36 33 37 - PG0 - PG1 - PE3/TIM1_BKIN - PE2/I2C_SDA
X X X X X X
X X
O3 X O3 X O1 X O1 X
X Port C6 X Port C7 X Port G0 X Port G1 X Port E3
SPI master out/ slave in SPI master in/ slave out
X X
O1 X
Timer 1 - break input
38 34
O1 T(1) X
Port E2 I2C data
26/56
STM8S103XX, STM8S105xx Table 5.
Pin number Type LQFP48 LQFP44 LQFP32
Pinouts and pin description
Pin description for STM8S105 MCUs (continued)
Main function (after reset) Port E0 Input Ext. interrupt High sink floating Output Alternate Default alternate function after function remap [option bit]
Speed
wpu
OD
Pin name
39 35 40 36
- PE1/I2C_SCL - PE0/CLK_CCO
I/O X I/O X
X X
X X
O1 T(1) X O3 X X
PP
Port E1 I2C clock Configurable clock output
41 37 25 PD0/TIM3_CC2
I/O X
X
X HS O3 X
TIM1_BKIN [AFR3]/ X Port D0 Timer 3 - channel 2 CLK_CCO [AFR2] X Port D1 SWIM data interface TIM2_CC3 [AFR1] ADC_ETR [AFR0] BEEP output [AFR7]
42 38 26 PD1/SWIM 43 39 27 PD2/TIM3_CC1 44 40 28 PD3/TIM2_CC2 45 41 29
I/O X I/O X I/O X
X X X X X X X
X HS O4 X X HS O3 X X HS O3 X X HS O3 X X X X O1 X O1 X O1 X
X Port D2 Timer 3 - channel 1 X Port D3 Timer 2 - channel 2 X Port D4 Timer 2 - channel 1 X Port D5 X Port D6 LINUART data transmit LINUART data receive
PD4/TIM2_CC1/BEE I/O X P I/O X I/O X I/O X
46 42 30 PD5/ LINUART_TX 47 43 31 PD6/ LINUART_RX 48 44 32 PD7/TLI
X Port D7 Top level interrupt
TIM1_CC4 [AFR4]
1. In the open-drain output column, `T' defines a true open-drain I/O (P-buffer and protection diode to VDD are not implemented)
27/56
Pinouts and pin description Table 6.
Pin number VQFN/LQFP32 TSSOP20 Type floating Pin name
STM8S103XX, STM8S105xx
Pin description for STM8S103 MCUs
Main function (after reset) Reset X X O1 X O1 X X Port A1 X Port A2 Resonator/ crystal in Resonator/ crystal out Port F4 Port E5 Input Ext. interrupt Output Alternate function Default alternate after function remap [option bit]
High sink
Speed
wpu
OD
(1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
3 4 5 6 7 8 9 -
NRST PA1/OSCIN PA2/OSCOUT VSS VCAP VDD PA3/TIM2_CC3/SPI_NSS PF4 PB7 PB6
I/O I/O X I/O X S S S I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X
X X X
PP X
Digital ground 1.8 V regulator capacitor Digital power supply X X X X X X X X X HS O3 X X X X X X O1 X O1 X O1 X O1 T SPI X Port A3 Timer 2 channel 3 master/sla ve select
X Port B7 X Port B6 X Port B5 I2C data
10 PB5/I2C_SDA 11 PB4/I2C_SCL PB3/TIM1_ETR PB2/TIM1_NCC3
O1 T(1) X Port B4 I2C clock X Port B3 X Port B2 Timer 1 external trigger Timer 1 - inverted channel 3
X HS O3 X X HS O3 X
15
-
PB1/AIN1/TIM1_NCC2
I/O X
X
X HS O3 X
Analog input 1/ X Port B1 Timer 1 - inverted channel 2 Analog input 0/ X Port B0 Timer 1 - inverted channel 1 X SPI master/slave select Timer 1 - channel 1 Timer 1 - channel 2
16
-
PB0/AIN0/TIM1_NCC1
I/O X
X
X HS O3 X
17 18 19
-
PE5/SPI_NSS PC1/TIM1_CC1 PC2/TIM1_CC2 PC3/TLI/TIM1_CC3/ USART_CK
I/O X I/O X I/O X
X X X
X HS O3 X X HS O3 X X HS O3 X
X Port C1 X Port C2
20
12
I/O X
X
X HS O3 X
Top level interrupt USART X Port C3 Timer 1 - channel clock 3
28/56
STM8S103XX, STM8S105xx Table 6.
Pin number VQFN/LQFP32 TSSOP20 Type floating Pin name
Pinouts and pin description
Pin description for STM8S103 MCUs (continued)
Main function (after reset) Input Ext. interrupt Output Alternate function Default alternate after function remap [option bit]
High sink
Speed
wpu
OD
21
PC4/AIN2/TIM1_CC4/ 13 CLK_CCO
I/O X
X
X HS O3 X
ConAnalog input 2 / figurable X Port C4 Timer 1 - channel clock 4 output X Port C5 X Port C6 X Port C7 Timer 2 - channel SPI clock 1 SPI master out/ slave in SPI master in/ slave out Configurable clock output
22 23 24
14 PC5/TIM2_CC1/SPI_SCK 15 PC6/SPI_MOSI 16 PC7/SPI_MISO
I/O X I/O X I/O X
X X X
X HS O3 X X HS O3 X X HS O3 X
25
-
PD0/TIM1_BKIN/CLK_CCO I/O X
X
X HS O3 X
Timer 1 - break X Port D0 input SWIM data interface
26
17 PD1/SWIM
I/O X
X
X HS O4 X
X Port D1
27
18 PD2/AIN3/TIM2_CC3
I/O X
X
X HS O3 X
Analog input 3 / X Port D2 Timer 2 - channel 3 Analog input 4 / ADC X Port D3 Timer 2 - channel external 2 trigger USART Timer 2 - channel clock/ X Port D4 BEEP 1 output X Port D5 Analog input 5 USART data transmit USART data receive
28
19
PD3/AIN4/TIM2_CC2/ADC_ I/O X ETR
X
X HS O3 X
29
PD4/TIM2_CC1/BEEP/ 20 USART_CK
I/O X
X
X HS O3 X
30
1
PD5/AIN5/USART_TX
I/O X
X
X
O1 X
31
2
PD6/AIN6/USART_RX
I/O X
X
X
O1 X
X Port D6 Analog input 6 Top level interrupt/ X Port D7 Timer 1 - channel 4
32
-
PD7/TLI/TIM1_CC4
I/O X
X
X HS O3 X
1. In the open-drain output column, `T' defines a true open-drain I/O (P-buffer and protection diode to VDD are not implemented)
PP
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Pinouts and pin description
STM8S103XX, STM8S105xx
5.2.1
Alternate function remapping
As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of 8 AFR (alternate function remap) option bits. Refer to Section 6: Option bytes on page 29. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. Alternate function remapping does not effect GPIO capabilities of the I/O ports (see GPIO section of the family reference manual, RM0016).
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STM8S103XX, STM8S105xx
Option bytes
6
Option bytes
Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the address shown in Table 7: Option bytes below. Option bytes can also be modified `on the fly' by the application in IAP mode, except the ROP and UBC options that can only be toggled in ICP mode (via SWIM). Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures.
Table 7.
Addr.
4800h
Option bytes
Option name Option byte no.
OPT0
Option bits 7 6 5 4 3
ROP[7:0]
2
1
0
Factory default setting
00h
Read-out protection (ROP) User boot code(UBC) Alternate function remapping (AFR) Watchdog option
4801h 4802h 4803h 4804h
OPT1 NOPT1 OPT2 NOPT2 AFR7 NAFR7 AFR6 NAFR6 AFR5 NAFR5 AFR4 NAFR4
UBC[7:0] NUBC[7:0] AFR3 NAFR3 AFR2 NAFR2 AFR1 NAFR1 AFR0 NAFR0
00h FFh 00h FFh
4805h 4806h 4807h 4808h 4809h 480Ah 480Bh 480Ch 480Dh 480Eh 487Eh 487Fh
OPT3 NOPT3
Reserved Reserved Reserved Reserved
LSI _EN NLSI _EN EXT CLK NEXT CLK HSECNT[7:0] NHSECNT[7:0] Reserved Reserved Reserved Reserved BL[7:0] NBL[7:0]
IWDG _HW NIWDG_ HW CKAWU SEL NCKAWUS EL
WWDG _HW NWWDG _HW PRS C1 NPR SC1
WWDG _HALT NWWG _HALT PRS C0 NPR SC0
00h FFh 00h FFh 00h FFh 00h FFh
Clock option
OPT4 NOPT4
HSE clock startup Reserved
OPT5 NOPT5 OPT6 NOPT6
Flash wait states Bootloader
OPT7 NOPT7 OPTBL NOPTBL
Wait state Nwait state
00h FFh 00h FFh
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Option bytes Table 8. Option byte description
STM8S103XX, STM8S105xx
Option byte no.
Description ROP[7:0] Memory readout protection (ROP) AAh: Enable readout protection (write access via SWIM protocol) Note: Refer to the family reference manual (RM0016) section on Flash memory readout protection for details. UBC[7:0] User boot code area For STM8S105 (page size 128 bytes): 00h: no UBC, no write-protection 01h: Page 0 and 1 defined as UBC, memory write-protected 02h to FFh: Pages 2 to 255 defined as UBC, memory write-protected For STM8S103 (page size 64 bytes): 00h: no UBC, no write-protection 01h: Page 0 and 1 defined as UBC, memory write-protected 02h to 7Fh: Pages 2 to 127 defined as UBC, memory write-protected Note: Refer to the family reference manual (RM0016) section on Flash write protection for more details. Note : This remapping applies to STM8S105. For STM8S103 alternate function remapping refer to Table 9 on page 34. AFR7Alternate function remapping option 7 0: Port D4 alternate function = TIM2_CC1 1: Port D4 alternate function = BEEP AFR6 Alternate function remapping option 6 0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4 1: Port B5 alternate function = I2C_SDA, port B4 alternate function = I2C_SCL AFR5 Alternate function remapping option 5 0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2, port B1 alternate function = AIN1, port B0 alternate function = AIN0 1: Port B3 alternate function = TIM1_ETR, port B2 alternate function = TIM1_NCC3, port B1 alternate function = TIM1_NCC2, port B0 alternate function = TIM1_NCC1 AFR4 Alternate function remapping option 4 0: Port D7 alternate function = TLI 1: Port D7 alternate function = TIM1_CC4 AFR3 Alternate function remapping option 3 0: Port D0 alternate function = TIM3_CC2 1: Port D0 alternate function = TIM1_BKIN AFR2 Alternate function remapping option 2 0: Port D0 alternate function = TIM3_CC2 1: Port D0 alternate function = CLK_CCO Note: AFR2 option has priority over AFR3 if both are activated AFR1 Alternate function remapping option 1 0: Port A3 alternate function = TIM2_CC3, port D2 alternate function TIM3_CC1 1: Port A3 alternate function = TIM3_CC1, port D2 alternate function TIM2_CC3 AFR0 Alternate function remapping option 0 0: Port D3 alternate function = TIM2_CC2 1: Port D3 alternate function = ADC_ETR
OPT0
OPT1
OPT2
OPT2 (cont'd)
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STM8S103XX, STM8S105xx Table 8. Option byte description (continued)
Description LSI_EN: Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock is available as CPU clock source IWDG_HW: Independent watchdog 0: IWDG Independent watchdog activated by software 1: IWDG Independent watchdog activated by hardware OPT3 WWDG_HW: Window watchdog activation 0: WWDG window watchdog activated by software 1: WWDG window watchdog activated by hardware WWDG_HALT: Window watchdog reset on halt 0: No reset generated on halt if WWDG active 1: Reset generated on halt if WWDG active EXTCLK: External clock selection 0: External crystal connected to OSCIN/OSCOUT 1: External clock signal on OSCIN
Option bytes
Option byte no.
OPT4
CKAWUSEL: Auto wake-up unit/clock 0: LSI clock source selected for AWU 1: HSE clock with prescaler selected as clock source for for AWU PRSC[1:0] AWU clock prescaler 00: Reserved 01: 16 MHz to 128 kHz prescaler 10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler
OPT5 OPT6 OPT7
HSECNT[7:0]: HSE crystal oscillator stabilization time This configures the stabilisation time to 0, 16, 256, 4096 HSE cycles. Reserved Reserved BL[7:0] Bootloader option byte This option is checked by the boot ROM code after reset. Depending on content of addresses 487Eh, 487Fh and 8000h (reset vector) the CPU jumps to the bootloader or to the reset vector. Refer to STM8S bootloader manual for more details.
OPTBL
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Option bytes
STM8S103XX, STM8S105xx
Table 9.
STM8S103x alternate function remapping bits.
Description AFR7Alternate function remapping option 7 0: TBD 1: TBD AFR6 Alternate function remapping option 6 0: TBD 1: TBD AFR5 Alternate function remapping option 5 0: TBD 1: Reserved AFR4 Alternate function remapping option 4 0: TBD 1: TBD AFR3 Alternate function remapping option 3 0: TBD 1: TBD AFR2 Alternate function remapping option 2 0: TBD 1: TBD AFR1 Alternate function remapping option 1 0: TBD 1: TBD AFR0 Alternate function remapping option 0 0: TBD 1: TBD
Option byte no.
OPT2
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STM8S103XX, STM8S105xx
Electrical characteristics
7
7.1
Electrical characteristics
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
7.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ).
7.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 C, VDD = 5.0 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ).
7.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
7.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10. Figure 10. Pin loading conditions
STM8 PIN
50pF
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Electrical characteristics
STM8S103XX, STM8S105xx
7.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11. Figure 11. Pin input voltage
STM8 PIN
VIN
7.2
Absolute maximum ratings
Stresses above those listed as `absolute maximum ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 10.
Symbol VDDx - VSS VIN
Voltage characteristics
Ratings Supply voltage (including VDDA and VDDIO)(1) Input voltage on true open drain pins (PE1, PE2)(2) Input voltage on any other pin(2) Min -0.3 VSS - 0.3 VSS - 0.3 Max 6.5 6.5 VDD + 0.3 50 mV 50 V Unit
|VDDx - VSS| Variations between different power pins |VSSx - VSS| Variations between all the different ground pins
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external power supply 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN36/56
STM8S103XX, STM8S105xx Table 11.
Symbol IVDD IVSS IIO
Electrical characteristics
Current characteristics
Ratings Total current into VDD power lines (source)(1) Total current out of VSS ground lines (sink)(1) Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on NRST pin Max. 60 60 20 - 20 4 4 4 20 mA Unit
IINJ(PIN)(2)(3)
Injected current on OSCIN pin Injected current on any other pin(4)
IINJ(PIN)(2)
Total injected current (sum of all I/O and control pins)(4)
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external supply. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VINTable 12.
Thermal characteristics
Ratings Storage temperature range Maximum junction temperature Value -65 to +150 C 150 Unit
Symbol TSTG TJ
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Electrical characteristics
STM8S103XX, STM8S105xx
7.3
Operating conditions
Table 13.
Symbol fCPU
General operating conditions(1)
Parameter Internal CPU clock frequency Conditions Min 0 3.0 LQFP48 Power dissipation at TA= 85 C for suffix 6 or TA= 125 C for suffix 3 LQFP44 LQFP32 VFQFN32 TSSOP20 Ambient temperature for 6 suffix version Maximum power dissipation Low power dissipation(2) -40 -40 -40 -40 -40 -40 Max 16 5.5 TBD TBD TBD TBD TBD 85 105 125 TBD 105 TBD C C C C C C mW Unit MHz V
VDD/VDD_IO Standard operating voltage
PD
TA Ambient temperature for 3 suffix version TJ Junction temperature range
Maximum power dissipation Low power dissipation (2) 6 suffix version 3 suffix version
1. TBD = to be determined. 2. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax
Figure 12. fCPUmax versus VDD
fCPU [MHz]
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
16
12 8 4 0 3.0
FUNCTIONALITY GUARANTEED @ TA -40 to 125 C
4.0
5.0
5.5
SUPPLY VOLTAGE [V]
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STM8S103XX, STM8S105xx
Electrical characteristics
7.3.1
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.
Table 14.
Symbol VIL VIH Vhys Rpu
I/O static characteristics(1)
Parameter Input low level voltage Input high level voltage Hysteresis(2) Pull-up resistor VDD = 5 V, VIN=VSS Fast I/Os Load = 50 pF Standard and high sink I/Os Load = 50 pF VSSVINVDD VSSVINVDD Injection current 4 mA 30 VDD = 5.0 V Conditions Min -0.3 V 0.7 x VDD 700 45 60 20 (3) 125 (3) Typ Max TBD VDD + 0.3 V Unit V V mV k ns ns
tR, tF
Rise and fall time (10% - 90%)
Ilkg
Input leakage current, analog and digital Analog input leakage current Leakage current in adjacent I/O(3)
1 (3)
A
Ilkg ana Ilkg(inj)
250 (3) 1(3)
nA A
1. TBD = to be determined. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. 3. Data based on characterization results, not tested in production.
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Electrical characteristics Figure 13. Typical VIL and VIH vs VDD @ 4 temperatures
6
STM8S103XX, STM8S105xx
-40C
5 4 VIL / V IH [V] 3 2 1 0 2.5 3 3.5 4 VDD [V] 4.5 5 5.5 6
25C 85C 125C
Figure 14. Typical pull-up resistance RPU vs VDD @ 4 temperatures
60 55 Pull-Up resistance [k ohm] 50 45 40 35 30 2.5 3 3.5 4 VDD [V] 4.5 5 5.5 6
-40C 25C 85C 125C
Figure 15. Typical pull-up current Ipu vs VDD @ 4 temperatures
140 120 Pull-Up current [A] 100 80 60 40 20 0 0 1 2 3 VDD [V]
Note: The pull-up is a pure resistor (slope goes through 0).
-40C 25C 85C 125C
4
5
6
40/56
STM8S103XX, STM8S105xx Table 15.
Symbol VOL
Electrical characteristics
Output driving current (standard ports)
Parameter Output low level with 4 pins sunk Output low level with 8 pins sunk Output high level with 4 pins sourced Conditions IIO = 4 mA,VDD = 3.3 V IIO= 10 mA,VDD = 5.0 V IIO = 4 mA, VDD = 3.3 V IIO = 10 mA, VDD = 5.0 V 2.1(1) V 2.8 Min Max 1000(1) mV 2000 Unit
VOH
Output high level with 8 pins sourced
1. Data based on characterization results, not tested in production
Table 16.
Symbol
Output driving current (true open drain ports)
Parameter Conditions IIO = 10 mA, VDD = 3.3 V Min Max 1500
(1)
Unit
VOL
Output low level with 2 pins sunk
IIO = 10 mA, VDD = 5.0 V IIO = 20 mA, VDD = 5.0 V
1000 TBD(1)
mV
1. Data based on characterization results, not tested in production
Table 17.
Symbol
Output driving current (high sink ports)
Parameter Output low level with 4 pins sunk Conditions IIO = 10 mA,VDD = 3.3 V IIO = 10 mA,VDD = 5.0 V IIO = 20 mA,VDD = 5.0 V IIO = 10 mA, VDD = 3.3 V IIO = 10 mA, VDD = 5.0 V IIO = 20 mA, VDD = 5.0 V 2.1(1) 4.0 3.3(1) V Min Max 1000(1) 800 1500(1) mV Unit
VOL
Output low level with 8 pins sunk Output low level with 4 pins sunk Output high level with 4 pins sourced
VOH
Output high level with 8 pins sourced Output high level with 4 pins sourced
1. Data based on characterization results, not tested in production
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Electrical characteristics
STM8S103XX, STM8S105xx
Figure 16. Typ. VOL @ VDD = 3.3 V (standard ports)
1.5 1.25 1 VOL [V] 0.75 0.5 0.25 0 0 1 2 3 IOL [mA] 4 5 6 7
Figure 17. Typ. VOL @ VDD = 5.0 V (standard ports)
1.5 1.25 1 VOL [V] 0.75 0.5 0.25 0 0 2 4 6 IOL [mA] 8 10 12
-40C 25C 85C 125C
-40C 25C 85C 125C
Figure 18. Typ. VOL @ VDD = 3.3 V (true open drain ports)
2 1.75 1.5 1.25 VOL [V] 1 0.75 0.5 0.25 0 0 2 4 6 IOL [mA] 8 10 12 14
Figure 19. Typ. VOL @ VDD = 5.0 V (true open drain ports)
2 1.75 1.5 1.25 VOL [V] 1 0.75 0.5 0.25 0 0 5 10 IOL [mA] 15 20 25
-40C 25C 85C 125C
-40C 25C 85C 125C
Figure 20. Typ. VOL @ VDD = 3.3 V (high sink ports)
1.5 1.25 1 VOL [V] 0.75 0.5 0.25 0 0 2 4 6 IOL [mA] 8 10 12 14
Figure 21. Typ. VOL @ VDD = 5.0 V (high sink ports)
1.5 1.25 1 VOL [V] 0.75 0.5 0.25 0 0 5 10 IOL [mA] 15 20 25
-40C 25C 85C 125C
-40C 25C 85C 125C
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STM8S103XX, STM8S105xx
Electrical characteristics
Figure 22. Typ. VDD - VOH @ VDD = 3.3 V (standard ports)
2 1.75 1.5 VDD - V OH [V] 1.25 1 0.75 0.5 0.25 0 0 1 2 3 IOH [mA] 4 5 6 7
Figure 23. Typ. VDD - VOH @ VDD = 5.0 V (standard ports)
2 1.75 1.5 VDD - V OH [V] 1.25 1 0.75 0.5 0.25 0 0 2 4 6 IOH [mA] 8 10 12
-40C 25C 85C 125C
-40C 25C 85C 125C
Figure 24. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports)
2 1.75 1.5 VDD - V OH [V] 1.25 1 0.75 0.5 0.25 0 0 2 4 6 IOH [mA] 8 10 12 14
Figure 25. Typ. VDD - VOH @ VDD = 5.0 V (high sink ports)
2 1.75 1.5 VDD - V OH [V] 1.25 1 0.75 0.5 0.25 0 0 5 10 IOH [mA] 15 20 25
-40C 25C 85C 125C
-40C 25C 85C 125C
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Electrical characteristics
STM8S103XX, STM8S105xx
7.3.2
Reset pin characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. Table 18.
Symbol VIL(NRST) VIH(NRST) VOL(NRST) RPU(NRST) VF(NRST) VNF(NRST)
NRST pin characteristics(1)
Parameter NRST Input low level voltage (2) NRST Input high level voltage (2) NRST Output low level voltage (2) NRST Pull-up resistor (3) NRST Input filtered pulse (4) NRST Input not filtered pulse (4) IOL=TBD mA 30 40 TBD TBD Conditions Min VSS TBD Typ
1)
Max TBD VDD TBD 60
Unit
V
k ns s
1. TBD = to be determined. 2. Data based on characterization results, not tested in production. 3. The RPU pull-up equivalent resistor is based on a resistive transistor 4. Data guaranteed by design, not tested in production.
Figure 26. Typical NRST VIL and VIH vs VDD @ 4 temperatures
-40C
6 5 4 VIL / V IH [V] 3 2 1 0 2.5 3 3.5 4 VDD [V] 4.5 5 5.5 6
25C 85C 125C
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STM8S103XX, STM8S105xx
Electrical characteristics
Figure 27. Typical NRST pull-up resistance RPU vs VDD @ 4 temperatures
60 NRST Pull-Up resistance [k ohm] 55
-40C 25C 85C 125C
50 45 40
35 30 2.5 3 3.5 4 VDD [V] 4.5 5 5.5 6
Figure 28. Typical NRST pull-up current Ipu vs VDD @ 4 temperatures
140 120 NRST Pull-Up current [A] 100 80 60 40 20 0 0 1 2 3 VDD [V] 4 5 6
-40C 25C 85C 125C
The reset network shown in Figure 29 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 14. Otherwise the reset is not taken into account internally. Figure 29. Recommended reset pin protection
VDD STM8
RPU
External reset circuit NRST 0.01F
Filter
Internal reset
45/56
Package characteristics
STM8S103XX, STM8S105xx
8
Package characteristics
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK(R) specifications are available at www.st.com.
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STM8S103XX, STM8S105xx
Package characteristics
8.1
8.1.1
Package mechanical data
LQFP package mechanical data
Figure 30. 48-pin low profile quad flat package (7 x 7)
A D D1 A1 b A2
e E1 E
L1 L
c
Table 19.
Dim.
48-pin low profile quad flat package mechanical data
mm Min Typ Max 1.60 0.05 1.35 0.17 0.09 9.00 7.00 9.00 7.00 0.50 0 0.45 3.5 0.60 1.00 7 0.75 0 0.0177 1.40 0.22 0.15 1.45 0.27 0.20 0.0020 0.0531 0.0067 0.0035 0.3543 0.2756 0.3543 0.2756 0.0197 3.5 0.0236 0.0394 7 0.0295 0.0551 0.0087 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0106 0.0079
A A1 A2 b C D D1 E E1 e q L L1
1. Values in inches are converted from mm and rounded to 4 decimal digits
47/56
Package characteristics Figure 31. 44-pin low profile quad flat package (10 x 10)
STM8S103XX, STM8S105xx
A D D1 A1 A2
b
e E1 E
L1 L h
c
Table 20.
Dim.
44-pin low profile quad flat package mechanical data
mm Min Typ Max 1.60 0.05 1.35 0.30 0.09 12.00 10.00 12.00 10.00 0.80 0 0.45 3.5 0.60 1.00 7 0.75 0 0.0177 1.40 0.37 0.15 1.45 0.45 0.20 0.0020 0.0531 0.0118 0.0035 0.4724 0.3937 0.4724 0.3937 0.0315 3.5 0.0236 0.0394 7 0.0295 0.0551 0.0146 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0177 0.0079
A A1 A2 b C D D1 E E1 e q L L1
1. Values in inches are converted from mm and rounded to 4 decimal digits
48/56
STM8S103XX, STM8S105xx Figure 32. 32-pin low profile quad flat package (7 x 7)
D D1 A1
Package characteristics
A A2
e
E1 E
b
L1 L h
c
Table 21.
Dim.
32-pin low profile quad flat package mechanical data
mm Min Typ Max 1.60 0.05 1.35 0.30 0.09 9.00 7.00 9.00 7.00 0.80 0 0.45 3.5 0.60 1.00 7 0.75 0 0.0177 1.40 0.37 0.15 1.45 0.45 0.20 0.0020 0.0531 0.0118 0.0035 0.3543 0.2756 0.3543 0.2756 0.0315 3.5 0.0236 0.0394 7 0.0295 0.0551 0.0146 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0177 0.0079
A A1 A2 b C D D1 E E1 e q L L1
1. Values in inches are converted from mm and rounded to 4 decimal digits
49/56
Package characteristics
STM8S103XX, STM8S105xx
8.1.2
QFN package mechanical data
Figure 33. 32-lead very thin fine pitch quad flat no-lead package (5 x 5)
Seating plane C A ddd C
A3
A1
D
e
9 8 16 17
E2
b
E
1
32
24
L
Pin # 1 ID R = 0.30
D2 Bottom view
L
42_ME
Table 22.
Dim.
32-lead very thin fine pitch quad flat no-lead package mechanical data
mm Min Typ 0.90 0.02 0.20 0.18 4.85 3.20 4.85 3.20 0.25 5.00 3.45 5.00 3.45 0.50 0.30 0.40 0.50 0.08 0.0118 0.30 5.15 3.70 5.15 3.70 0.0071 0.1909 0.1260 0.1909 0.1260 0.1969 0.1358 0.0197 0.0157 0.0197 0.0031 Max 1.00 0.05 Min 0.0315 inches(1) Typ 0.0354 0.0008 0.0079 0.0098 0.1969 0.0118 0.2028 0.1457 0.2028 0.1457 Max 0.0394 0.0020
A A1 A3 b D D2 E E2 e L ddd
0.80 0
1. Values in inches are converted from mm and rounded to 4 decimal digits 1. TBD = to be determined.
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STM8S103XX, STM8S105xx
Package characteristics
8.1.3
TSSOP package mechanical data
Figure 34. TSSOP 20-pin, 4.40 mm body, 0.65 mm pitch
D
20
11
c
E1 E
1
10
A1 A CP b e A2
L L1
TSSOP20-M
Table 23.
Dim.
TSSOP 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data
mm Min Typ Max 1.2 0.05 0.8 0.19 1 0.15 1.05 0.3 0.1 0.09 6.4 6.2 4.3 0.45 6.5 6.4 4.4 0.65 0.6 1 0 8 0 0.2 6.6 6.6 4.5 0.75 0.0035 0.252 0.2441 0.1693 0.0177 0.2559 0.252 0.1732 0.0256 0.0236 0.0394 8 0.002 0.0315 0.0075 0.0394 Min inches(1) Typ Max 0.0472 0.0059 0.0413 0.0118 0.0039 0.0079 0.2598 0.2598 0.1772 0.0295
A A1 A2 b CP c D E E1 e L L1 a
1. Values in inches are converted from mm and rounded to 4 decimal digits
51/56
Ordering information
STM8S103XX, STM8S105xx
9
Ordering information
Figure 35. STM8S103/105 access line ordering information scheme
Example:
STM8
S
103
F
3
P
6
B
Product class
STM8 microcontroller
Family type
S = Standard
Sub-family type
105 = intermediate peripheral set 103 = small peripheral set
Pin count
F = 20 pins K = 32 pins S = 44 pins C = 48 pins R = 64 pins
Program memory size
2 = 4 Kbytes 3 = 8 Kbytes 4 = 16 Kbytes 6 = 32 Kbytes
Package type
P = TSSOP U = VFQFPN T = LQFP
Temperature range
6 = -40 C to 85 C
Package pitch
no character = 0.5 mm B = 0.65 mm C = 0.8 mm
Packing
no character = tray or tube TR = tape and reel For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to you.
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STM8S103XX, STM8S105xx
STM8 development tools
10
STM8 development tools
Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer.
10.1
Emulation and in-circuit debugging tools
The STM8 tool line includes the full-featured STice emulation system offering a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller. For improved cost effectiveness, STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers.
STice key features

Occurrence and time profiling and code coverage (new features) Advanced breakpoints with up to 4 levels of conditions Data breakpoints Program and data trace recording up to 128 K records Read/write on the fly of memory during emulation In-circuit debugging/programming via SWIM protocol 8-bit probe analyzer 1 input and 2 output triggers Power supply follower managing application voltages between 1.62 to 5.5 V Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements Supported by free software tools that include integrated development environment (IDE), programming software interface and assembler for STM8
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STM8S103XX, STM8S105xx
10.2
Software tools
STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST visual develop (STVD) IDE and the ST visual programmer (STVP) software interface. STVD provides seamless integration of the cosmic C compiler for STM8, which is available in a free version that outputs up to 16 Kbytes of code.
10.2.1
STM8 toolset
STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes: ST visual develop - Full-featured integrated development environment from ST, featuring

Seamless integration of C and ASM toolsets Full-featured debugger Project management Syntax highlighting editor Integrated programming interface Support of advanced emulation features for STice such as code profiling and coverage
ST visual programmer (STVP) - Easy-to-use, unlimited graphical interface allowing read, write and verify of your STM8 microcontroller's Flash memory. STVP also offers project mode for saving programming configurations and automating programming sequences.
10.2.2
C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. Available toolchains include:

Cosmic C compiler for STM8 - Available in a free version that outputs up to 16 Kbytes of code. For more information, see www.cosmic-software.com. Raisonance C compiler for STM8 - Available in a free version that outputs up to 16 Kbytes of code. For more information, see www.raisonance.com. ST7/STM8 assembler linker - Free assembly toolchain included in the ST7/STM8 toolset, which allows you to assemble and link your application source code.
10.3
Programming tools
During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming your STM8. For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family.
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Revision history
11
Revision history
Table 24.
Date 05-Jun-2008 23-Jun-2008
Document revision history
Revision 1 2 Initial release. Corrected number of high sink outputs to 9 in I/Os on page 1. Updated part numbers in Table 2: STM8S103/105 access line features on page 7. Changes
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